(a) Field of the Invention
This invention relates to the operation of a non volatile flash memory cell and in particular to erasing the cell by manipulating the stored charge within.
(b) Description of the Related Art
A flash EEPROM cell is a semiconductor device having non volatile memory properties which can be electrically programmed and erased. The non volatile memory properties enable the device to retain stored information once the power is turned off. The information is in the form of electrons stored within the floating gate. Devices of this type are described in U.S. Pat. Nos. [1] 4,698,787 and [2] 5,077,691, all of which are incorporated herein by reference. Other similar devices of this type are also described in U.S. Pat. Nos. [3] 5,243,559, [4] 5,361,235, [5] 5,457,652 and [6] 5,790,460, all of which are incorporated herein by reference.
Flash EEPROM devices are electrically erasable, programmable, read-only memory devices, which are electrically programmed and erased using on chip high and negative voltage generation circuitry. Data is stored in a binary format in the cell in a manner that the cell is set to a programmed state and reset to an erased state. Programming the cell is accomplished by storing electrons in the floating gate usually by means of tunneling or hot carrier injection. Erasing the cell is done by removing the charge usually by means of tunneling.
In the prior art there are several erase techniques for a flash memory mostly based on the physical phenomena of charge tunneling through a potential barrier. Implementation of tunneling erase techniques requires the usage of large electrical field across the dielectric between the floating gate and the well. These high electrical fields are known to generate reliability issues that degrade the quality of the dielectric which would eventually cause device failure. As devices advance further into sub micron dimensions, the intensity of the electric fields grow higher to become a dominating factor limiting the device scale down process.
Conventional flash cell erase is achieved by application of a large negative voltage to the control gate and simultaneous application of a moderate positive voltage to the source region. This technique is usually referred to as Negative Gate Source Erase (NGSE). A variation to this method uses both source and drain regions in the erase process at the same time with the exact same bias operation methodology. FIG. 1 shows a prior art flash cell using Fowler-Nordheim tunneling for NGSE. The cell 9 is fabricated on a P-type substrate 10 which is maintained at ground potential, while a large negative potential Vg of about −11V is applied to the control gate 11 and simultaneously a positive potential Vs of about 5V is applied to the source region 12, fabricated from an n+ type semiconductor inside an n-region 15. The drain region 8 is kept floating throughout the process. The electrical field formed across the dielectric layer 19 between the floating gate and the substrate would yield a tunneling current draining the electrons stored in the floating gate.
This erase scheme suffers from a reliability issue caused by “hot hole” injection from the substrate 10 into the tunneling dielectric 19 [I-III]. Since the source region 16 is reversed biased during the erase operation, a band to band tunneling current is present at the surface 17. This tunneling current produces energetic holes that are attracted by the floating gate to source electric field and have a probability for tunneling into the floating gate. This probability is directly related to the magnitude of this electric field. Thus, the “hot hole” current has a strong dependency on the electric field and imposes yet another limit on device sizing as well as on operation voltage levels. The stronger the electric field the larger the tunneling current and vice versa. These “hot hole” cause damage to the semiconductor insulator interface 17 and the dielectric layer 19 by generating interface states and inter dielectric traps. Given enough time, these traps would line up to cause a breakdown of the insulator layer and rend the device useless, a phenomena known as Time Dependent Dielectric Breakdown (TDDB). TDDB theory presents an exponential dependency of the breakdown probability and time to failure of the device on the electrical field strength and stress duration. Attempting to prolong the time to failure by lowering the electric field would result in exponentially longer erase times since the Fowler-Nordheim tunneling current density has an inverse exponential dependency as well and would decrease with lower electric fields. Furthermore, by using NGSE the hot hole tunneling current is localized beneath the source and floating gate overlapping area and the likelihood of the dielectric traps to line up and form a breakthrough path is high.
Referring to FIG. 2, another prior art erase technique is presented using a p-type well structure 24. The p-well 24 is contacted using a p+ region 29 and formed in a deep n-type well 25. The n-well 25, which may be contacted using an n+ region 36, is formed within a p-type substrate 23. This erase technique uses a large negative bias potential Vg applied to the control gate 21 of about −11V while simultaneously applying a positive bias potential Vb of about 5V to the p-well 24 via the well terminal 29. The charge storing layer 28, also referred to as floating gate, lies beneath the control gate 21 with a dielectric 34 forming an intermediate insulating layer. Usually the p-type substrate 23 is grounded and the n-well 25 is kept floating during the erase operation. The source region 30 and the drain region 31 are either kept floating [3] or at the same potential as the p-well 24 [6], causing the electrons stored in the floating gate 28 to tunnel vertically through the tunneling oxide 33 and into the channel region 22. This prior art erase technique is commonly referred to as Negative Gate Channel Erase (NGCE).
The NGCE technique suffers from a different reliability problem. Since the charge is erased into the channel region 22, by using high electric fields a high energy, a tunneling electron could impact ionize the semiconductor interface to generate an electron hole pair. This energetic hole, as in the previously presented NGSE method, would be attracted by the same high electric field and tunnel back through the dielectric layer 34 into the floating gate 28. This “hot hole” tunneling current would have the same affect on the dielectric quality and cause degradation over time. However, since in this case, the surface states and inter dielectric traps are distributed along the entire channel length, most of the performance penalty would be manifested in cell read current degradation and reduced programming performance. The impact on programming efficiencies results from the fact that these traps interfere with the hot carrier injection process.
Another prior art variation for NGCE technique [6] utilized the same biasing potential application for the p-type well 24 and the source region 30. This technique attempts to minimize the reliability problems induced by hot hole injection by applying the same potential bias to the source and the well, thus minimizing the band to band tunneling the would otherwise occur at the source dielectric interface 26. This prior art technique, however, does not eliminate the need for using high electric field across the dielectric during erase and the resulting TDDB and performance degradation issues.
FIG. 3 shows the biasing voltage waveform time dependence used to operate the flash cell during erase in the prior art. All prior art techniques use an operation methodology that dictates a simultaneous application of the bias pulses for the control gate and the well either with or without the source and drain regions (the latter are either operated in the same manner as the well or kept floating). Since tunneling is the main mechanism used in erasing the cell it is necessary to generate a strong electrical field over the dielectric during erase. As a result, the potential difference between the control gate and the well should be the highest obtainable. The well bias waveform has a finite rise and fall times and a positive polarity while the control gate bias waveform simultaneously assumes a negative polarity. The effective erase time for tunneling to occur is the actual overlap time of these two waveforms when the electric field is maximized. All prior art techniques attempt to maximize the overlap time between these waveforms in order to get the maximal electrical field during the erase sequence making them highly vulnerable to the above mentioned reliability issues. Another drawback of this prior art operation methodology is that the biasing scheme would also yield an electric field across the control gate to floating gate dielectric that would induce charge tunneling from the former to the latter. This tunneling current would interfere with the erase process by adding charge to the floating gate.
When inter dielectric charge traps are present under the floating gate (as shown in FIG. 4 as 41b), the tunneling current from the floating gate to the well has two major components: the direct tunneling component (marked 37b as in FIG. 4) and the indirect tunneling component. The direct component is that of charge having sufficient energy to overcome the potential barrier and tunnel to the well, also commonly referred to as Fowler-Nordheim tunneling or “Field Emission”. The indirect component or trap assisted tunneling comprises of two stages. The first stage being the tunneling of charge from the floating gate to the trap (marked 38b in FIG. 4) and the second being tunneling of the same charge from the trap to the well (marked 39b in FIG. 4). The tunneling mechanism is well known to be of a random nature and of having a probability function dependency given by
                    J        ∝                                            P                              1                ⁢                                  (                                      x                    t                                    )                                                      ·                          P                              2                ⁢                                  (                                      x                    t                                    )                                                                                        P                              1                ⁢                                  (                                      x                    t                                    )                                                      +                          P                              2                ⁢                                  (                                      x                    t                                    )                                                                                        (        1        )            
Where Xt indicate the trap location measured from the floating gate to dielectric interface, P1 is the tunneling probability of the first stage and P2 is the tunneling probability of the second stage. FIG. 8 shows the probability function dependence on trap location. Referring to FIG. 8, the two stage indirect tunneling current probability components P1, P2 and (P1+P2) as a function of a trap location within the dielectric is depicted. The probability P1 is the tunneling probability of the first stage, gate to trap, as a function of trap location and is of inverse exponential nature. The probability P2 is the tunneling probability of the second stage, trap to well, as a function of trap location and is of inverse exponential nature as well. Both components P1 and P2 display an inverse exponential behavior, where the probability for tunneling to occur decreases exponentially with the distance. The component (P1+P2) has local minima at the dielectric width mid point suggesting that traps located next to this location would have a larger contribution to the indirect tunneling current. The reasoning is that although traps located inside the dielectric near the floating gate (marked 40b in FIG. 4) have a higher tunneling probability P1 in the first stage, their second stage tunneling probability P2 is considerably lower and vice versa for traps located close to the well (marked 42b in FIG. 4). Since the overall tunneling probability is a multiplication of these two elements the smaller one would dominate the outcome.
Mobile positively charged ions within the dielectric are also known to degrade the performance of MOS structures by reacting to the gate voltage potential and having charge trapping and releasing properties [IV-V]. FIG. 7 shows how such positively charged mobile traps within the dielectric are displaced when a voltage potential is applied to the gate due to electric field rejection. Referring to FIG. 7, a structure 50 having a control gate 52 and an underlying dielectric layer 54 is depicted. The dielectric layer contains positively charged mobile traps (ions) 53. The movement of these traps due to positive bias 51 application to the gate is depicted using directional arrows. In the same manner, when a flash cell is operated according to prior art as described in FIG. 3, such traps would assume a fixed position in the dielectric during the erase process closer to the floating gate due to the negative bias on the control gates. In this new location the tunneling probability of the above mentioned indirect current component would be lower and as a result this component would decrease.
The background and associate prior art erase procedures are described in the following publications: [I] Witters, et al., “Degradation of Tunnel Oxide Floating Gate EPROM Devices and Correlation With High-Field-Current-Induced Degradation of Thin Gate Oxides”, IEEE Transactions On Electron Devices, Vol. 36, No. 9, September 1989, p. 1663. [II] Chun, et al., “Lateral Distribution of Erase Induced Hole Trapping and Interface Traps in Flash EPROM NMOSFET Devices”, IEEE Semiconductor Interface Specialists Conference, 1996. [III] A. Yokozawa, et al., “Investigation for Degradation of the Retention Characteristics due to Oxide Traps Induced by Hole Injection”, NVMSW proc. 1998 pp. 83-85. [IV] S. G. Dmitriev, Y. V. Markin, “Macroscopic Ion Traps at the Silicon Oxide Interface”, Semiconductor, Vol. 32, pp. 625-628, June 1988. [V] Vertoprakhov et al., “The effect of mobile charge in silicon dioxide on the surface states density of mos structure”, Russian Physical Journal, Vol. 19, pp. 378-379.